How Synopsys and Cadence are fueling the semiconductor industry's growth engine

Chris Zeoli
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Cadence and Synopsys are providers of EDA (electronic design automation) design software for the semiconductor industry, a critical and highly value-add piece of the chip design workflow. Both are well positioned to capitalize on the durable growth trends of growing chip complexity, expansion of in-house application-specific integrated circuit (ASIC) design teams and the AI capex cycle boom. Both companies are expected to grow at 15-20%+ CAGRs over the next 5 years, which is significantly above the overall growth of the semiconductor industry.

In fact, Cadence and Synopsys are some of the most durable, attractive businesses in all of software and technology.

I collaborated with Calvin Zeng, a partner at Dandelion Capital Management, to analyze these two companies and discuss their advantages and challenges.

Technology Overview

EDA tools have revolutionized chip design by digitizing the process and providing critical capabilities for simulation, design and verification. As chip complexity grows, EDA tools become increasingly valuable.

Historically, large OEMs developed EDA tools in-house, but the rise of the commercial ASIC industry in the 1980s led to the emergence of specialized EDA providers. Today, Synopsys, Cadence and Siemens EDA dominate the market.

EDA software is a collection of tools that address different aspects of the chip design process. Simulation software predicts circuit behavior, design solutions help create the physical circuit elements, and verification systems ensure the design is correct and manufacturable.

Design for Manufacturing (DFM) tools, closely tied to the foundry's process design kits (PDKs), are crucial for ensuring the chip design meets manufacturing requirements. Once the chip design is finalized using EDA tools, it moves to the production stages, including mask creation, wafer fabrication, packaging, testing and assembly.

Source: Cadence

Decoding the business models

Both Cadence and Synopsys make most of their revenue through subscription-based sales of their software suites. They both have an opaque pricing process, but I’ve been able to roughly piece together what they charge. That said, there seem to be a lot of highly customized and bespoke agreements with individual customers.

The most common pricing scheme is seat-based pricing. These are fixed-length contracts (generally 3 years) that give a certain number of licenses to a specific set of tools (e.g., 5 simulation licenses, 3 design licenses and 1 verification license, each at their own price points).  

Pricing is highly customized based on the specific tools required by each customer. It's important to note that EDA software is not a one-size-fits-all solution, but rather a collection of specialized tools. While there is a general price list that helps guide the overall package pricing, the final cost is tailored to the unique needs of each customer.

For some large customers, EDA vendors occasionally offer full-service pricing, which provides all-you-can-eat access to the entire toolset without restrictions on the number of seats. According to a Director of Semis at Azure, Synopsys made such an offer to Intel, with a fixed price exceeding $1 billion. Similarly, Samsung reached a comparable agreement with Mentor Graphics about eight years ago.

These comprehensive deals are typically the result of complex contract negotiations that take into account factors such as the customer-vendor relationship, anticipated tool usage and seat growth, as well as the customer's financial health and willingness to invest in the EDA tools.

The largest chip design companies, such as NVIDIA, AMD and Broadcom, are likely to have similar full-service pricing contracts with EDA vendors. As these companies' research and development budgets grow, driven by the current AI capex investment cycle, we anticipate corresponding price increases in their EDA contracts.

For shorter-term engagements, or as an addendum to the standard seat-based pricing, EDA vendors sometimes use a flexible token-based pricing model. Customers pay upfront for a specific number of tokens which can be used for different tools on an as-needed basis.  

Consumption of these tokens is typically linked to specific projects and presents an opportunity for Cadence and Synopsys to upsell additional products to their customers. Design projects often require a unique combination of tools, leading to the consumption of tokens. Projects may also necessitate the use of IP, which is a part of both Cadence and Synopsys's IP business. This further drives token usage and revenue growth.

I expect consistent token-based spend to translate into price increases for larger contracts in the next renewal cycle. Again, with the growing complexity of chip design and both companies’ investment in AI tools (discussed later), I think this upsell motion has many legs and will continue to drive top-line growth for both Cadence and Synopsys.

Taking all these pricing schemes into account, I think the net result is that EDA revenue is largely tied to the number of chip designers employed (per seat fee) and flexes up on increasing complexity of the chip (number of tools needed at higher price points) and IP requirements (upsell of their IP offerings).

Arm's F-1 filing provides valuable insights into the rapidly increasing cost of chip design. The company reported significant cost increases at recent technology nodes, particularly with the transition to Extreme Ultraviolet Lithography (EUV). Furthermore, Arm anticipates another substantial cost jump at the 2-nanometer node, as the industry transitions to Gate-All-Around (GAA) transistor technology.

Source: Arm F-1

Because of the leverage to the industry trends of increasing chip complexity and growth in chip designer HC (roughly, more transistors equal a larger team of design engineers and more software to run an increasing number of simulations to verify the design), both Cadence and Synopsys have been able to grow consistently at ~10-15% yearly over the last 10 years.

As a top-down view of the broader industry, EDA and IP capture 2-3% of semiconductor spend.

Source: Synopsys

A commonly cited barometer for EDA spend is the continual growth in the R&D budget across semiconductor design companies. We’ve benchmarked Cadence and Synopsys revenue against R&D spend of the five largest semis companies and found it to be a good rough heuristic. Cadence and Synopsys software spend has grown to 30% of the top five semi companies’ R&D.

An uptick in R&D spend starting in 2021 corresponded with a similar rise in growth rates. With the AI race and associated capex cycle kicking off, companies are continually revising their R&D budgets upwards (I think Wall Street estimates across the board are too low on R&D, based on my work on NVIDIA and Advanced Micro Devices).  

EDA has been capturing a growing share of R&D spend. However, this trend may be influenced by the entry of hyperscalers and automotive companies establishing their own internal design teams, which could potentially skew the data.

Cadence versus Synopsys

It's important to recognize that Cadence and Synopsys offer comparable tools and solutions. The majority of large customers purchase software from both companies, aiming to create an optimal toolset by selecting the best options from the comprehensive product suites offered by Synopsys, Cadence and Mentor. This approach allows customers to leverage the competition between these EDA providers to negotiate favorable pricing and terms.

There is some degree of preference based on specific industry verticals, or the subclass of the toolset where one provider may be favored over the other, but in general, the market share between the EDA players tends to be quite entrenched.

As a result of the stable market share, competitive dynamic, overlapping customer base and similarity in product offering, the share price performance of Cadence and Synopsys are highly correlated.

The biggest difference comes from their relative valuations, where Cadence trades at a premium (48x P/E) versus Synopsys (42x P/E) due to its higher operating margin (30% versus 20-25%). This is largely because Synopsys has a larger lower-margin IP business (25% versus 10%).

We don’t really have a hard view on whether the IP business makes Synopsys a better or worse buy than Cadence. My view is that IP is a natural extension of the design product that is offered. Alongside growing chip complexity is a greater need for off-the-shelf IP, especially as design costs at the leading edge grow higher — so I’d expect the IP revenue of both to grow in line with their broader EDA recurring software revenue.

As the semiconductor industry shifts towards chiplet architectures, Synopsys' extensive IP portfolio may yield higher ROI. Chiplet-based designs allow for the mixing and matching of IP blocks at different technology nodes, which means IP will no longer require constant updates to keep pace.

That said, I think that’s a small part of the overall picture, and absent any unexpected developments, I think the stock prices will continue to be highly correlated.

Cadence overview

Cadence was founded in 1987 and segments its business into functional verification, digital IC (digital), custom IC (analog), system design and semiconductor IP. They have roughly 85% recurring revenue with approximately $4 billion in 2023 revenue, growing at around 12% compound annual growth rate over the last 5 years.

Source: Cadence investor presentation 2023

Cadence has a notably smaller IP portfolio compared to Synopsys and places less emphasis on it relative to their core EDA software portfolio. Instead, they concentrate on differentiated IP, as shown by their recent acquisition of Rambus' leading-edge SerDes IP assets.

“In Cadence's business we have some IP, we focus on differentiated IP, because the important thing there for us is just to have a seat at the table. It's the least profitable business at Cadence. It's about 10% of the business.” — Cadence CEO Anirudh Devgan, 2023 Nasdaq Investor Conference (Dec 2023)

Cadence’s AI offering is called, which is a set of tools that help automate PCB design and chip design flow, among others.

Synopsys overview

Synopsys was founded in 1986 and segments its business into design revenue (65%), IP (25%) and its application software testing business (10%, currently in a sale process).

Source: Synopsys investor relations deck

 Synopsys has taken a different approach than Cadence, aggressively investing in its IP licensing business. Through numerous acquisitions, Synopsys has amassed an extensive portfolio of IP blueprints, making it the largest licensor of IP in the industry, even surpassing Arm. But despite its leading position in IP licensing, Synopsys still generates significantly lower royalty revenues compared to Arm.

Source: IPnest 2023

Source: SemiWiki


Source: SemiWiki


Their AI software suite is called, which is a set of tools focused on optimizing specific pieces of the EDA workflow (e.g., verification of design spaces, power flow, etc.). It generally feels more fleshed out than Cadence’s competing offering, though that may be because Synopsys takes a more promotional stance towards their AI offering.

Key debates

1. Long-term growth potential

The biggest debate is around whether we will see a return to the 15-20% growth rates that the two companies experienced in the COVID period, or a return to the historical 10-15% growth (currently being modeled by Street). This was a part of the reaction to the somewhat disappointing FY 24 guidance by Cadence, which triggered a 5x re-rating down on both stocks in early March.

We believe the semiconductor industry will continue to grow long-term. The trends that drove the increased spend on Cadence and Synopsys are not ebbing and in many ways are only intensifying. This is furthermore juxtaposed against a massive AI capex and demand cycle that has many trickle-down effects on the R&D budgets of chip designers. The automotive sector, though small right now, is the next leg of design activity that should significantly pick up in the latter half of this decade, with OEMs investing in custom ASIC designs.

On the complexity of chips, the industry has a well-defined roadmap for the next decade, which includes the adoption of GAA and Complementary Field-Effect Transistor (CFET) technologies. These advancements involve 3D-stacked transistors smaller than 1 nanometer, which will continue to drive complexity and increase design costs at the leading edge. We also have a wave of incoming chip innovations (e.g., 3D chiplet architecture, backside power, etc.) that will continually increase the design complexity and provide more opportunities for upsell and pricing increases of higher value-add software tools in the EDA process flow.  

In general, it is cheaper for a customer to invest in productivity-enhancing technology rather than hire more chip designers, and I’d expect EDA to capture a growing percentage of the R&D budget as AI offerings continue to get fleshed out.

Many companies, including hyperscalers working on AI projects and automotive manufacturers like Tesla, are increasingly establishing their own in-house chip design teams. This trend towards custom silicon development will lead to a growing demand for EDA software licenses, as these companies require additional tools and resources to support their design efforts.

ASICs and specialized chips that are closely integrated with software development are crucial for maintaining the pace of Moore's Law. As highly generalizable chips begin to fall behind on the power/efficiency curve, particularly given the stringent power and durability requirements in the automotive industry and the intensive computational demands of AI applications, custom silicon solutions become increasingly important.

It’s clear that many companies now view in-house design capabilities alongside their software capabilities as a necessity to stay competitive. This increases both the number of projects as well as the number of chip designers.

While the chip complexity trend has been going on for a while now, the trends around in-house ASIC design work accelerated in 2023 and will only continue to grow in importance over the next decade.

In my opinion, the combination of increasing design complexity and the trend towards custom silicon will propel long-term growth rates to around 15-20%, surpassing current Wall Street expectations, which anticipate a reversion to the historical norm observed between 2017 and 2020.

2. The impact of AI

As discussed earlier, the AI capex spend significantly influences semiconductor spending, which in turn drives R&D budgets and consequently, EDA expenditures. I also think that the investment in AI (both models and compute infrastructure) will be very beneficial for the value-add of the EDA product suite and corresponding pricing.

Both Synopsys and Cadence, over the last year, have both been promoting their LLM-driven offering, bundling their AI products into “AI-named” product suites and hinting at potential revenue uplift from upsell of these products (Synopsys is more promotional than Cadence).

I’m a bit mixed on the near-term impact of LLMs on their ability to drive meaningful pricing increases. We’re still in the early stages of commercial viability of LLMs as CoPilots (see Microsoft Copilot reception and development). Over the long run, I think there is a place for a chip design CoPilot that can help designers in their tasks, but I don’t think it is nearly as revolutionary — or will lead to as many productivity improvements — given the specialized and highly technical nature of chip design. LLMs are good for broad generalizable tasks, but less so for very specific and precise knowledge.

I’m more enthusiastic about the innovations in compute infrastructure that are occurring. Many of the highest value-adds in the chip design workflow come from optimization tools — often big data/reinforcement-learning problems that are very compute-intensive. We are already seeing innovations in the DFM process with cuLitho, NVDA’s computational lithography program.

Alongside GenAI, that is a huge amount of drag-along investment in the infrastructure and ecosystem of AI, which Synopsys and Cadence can benefit from. The two companies can develop tools that further optimize the chip design process that represent hard ROI and will drive continual, justified pricing increases. Skimming through the “AI” product portfolio, it’s clear that both are investing heavily in it as behind the surface-level CoPilot tools is a broader suite of deep-learning tools that further optimize the chip design process.

3. China

China accounts for 18% of Cadence's revenue and around 16% of Synopsys' revenue, making it a crucial market for both companies. However, the sustainability of spending from this region remains a significant question. Although the actual impact of export restrictions has been limited so far, with the most notable consequence being Huawei's removal as a customer, China is actively investing in its domestic EDA ecosystem. Empyrean, the largest Chinese EDA vendor, is still relatively small compared to Synopsys and Cadence.

My view is that the China risk is minimal, as EDA tools are extremely complex and still growing in complexity.

Furthermore, I think that the risk of restrictions is low, as the exports are ostensibly focused on specific capabilities (e.g., AI) or in manufacturing capabilities (e.g., no EUV for China). I generally agree with the remarks Anirudh Devgan made at the Wells Fargo conference:

“If you look at the last 5 years, our China business is growing like a 20%-plus CAGR. So I expect China to be a good business long term. There are two kinds of questions we get. One is on local development in China, there are some companies trying to write EDA tools. And second is US regulation. The US regulation is a long topic, but in summary, the impact to Cadence is pretty limited. I mean, those regulations are targeted mostly towards manufacturing in China at this point. And even if you go to China, all the big companies are not manufacturing in China, they are manufacturing in TSMC or Samsung. So we are more connected to the design activity. So now the second part is, will there be local competition in China? Because at this point, we are in a very strong position. So these things take a long time. There are some very small companies doing point tools. But to really do a full flow at 3-nanometer, of course we watch it very carefully, but I’m not concerned that this is a short to midterm issue with local competition in China. So overall, I’m pretty optimistic about the China market, yes.”

EDA giants poised to capitalize on semiconductor industry boom

Synopsys and Cadence are well-positioned to benefit from the semiconductor industry's rapid growth and the increasing demand for advanced chip design tools. The rise of AI, the need for custom silicon and the growing complexity of chip design all contribute to a strong outlook for these EDA giants.

As the semiconductor industry continues to evolve and innovate, Synopsys and Cadence are poised to play a critical role in enabling the next generation of chip design.

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